In a semiconductor storage device such as a NAND EEPROM, selection gate transistors are provided on both ends of a memory cell array so as to select memory cells, conventionally. A hard mask used to form each gate electrode of the memory cells is processed while using a sidewall as a mask (a sidewall transfer method). Meanwhile, a hard mask used to form each gate electrode of the selection gate transistors is processed while using a resist film according to a lithography technique as a mask. In the lithography technique, it is necessary to design the space width between each selection gate transistor and the memory cell array to be larger than a distance between the memory cells so as to secure an alignment margin.
However, if the space width between each selection gate transistor and the memory cell array is large, a phenomenon (substrate gouging) occurs that a semiconductor substrate is gouged in a space area between the selection gate transistor and the memory cell array at the time of processing the gate electrodes of the selection gate transistors and the memory cells by RIE (Reactive Ion Etching).
Such substrate gouging causes an increase in resistances of diffusion layers in the space area between the selection gate transistor and the memory cell array and reduction in a cell current. Furthermore, if the space width between the selection gate transistor and the memory cell array is large, there is also a problem that a chip size increases.